Basic version MCS–51 Brief information. Modern 8-bit microcontrollers (MCs) have such real-time control resources, for which previously expensive multi-chip layouts in the form of separate microcomputer boards were used, namely:

● have sufficient memory capacity, its physical and logical division into program memory and data memory (Harvard architecture) and a command system aimed at executing control algorithms;

● include all devices (processor, ROM, RAM, input/output ports, interrupt system, means for processing bit information, etc.) necessary to implement a minimal configuration microprocessor control system. In the 70s of the last century the company Intel a family of 8-bit microcontrollers MCS-48, united by a number of common features (bit capacity, command system, set of main functional blocks, etc.), has been developed and launched into industrial production. The basic version of this family includes:

● 8-bit processor;

● internal program memory (1/2/4K bytes);

● internal data memory (64/128/256 bytes);

● up to 27 internal and 16 external I/O lines;

● one 8-bit timer-counter;

● single-level interrupt system with two request sources. In 1980, the same company developed a new family of eight-bit microcontrollers, MCS-51, which is compatible with the architecture of the MCS-48 family, but has greater capabilities.

The architecture of the MCS-51 family turned out to be so successful that it is still one of the standards for 8-bit MKs. Therefore, the object of study was chosen to be microcontrollers of this family, which are widely used in relatively simple control systems.

Various program preparation tools have been developed for the MCS-51 family (compilers, hardware-software emulators, etc.) and there is a large number of libraries of standard routines. The family includes various modifications of microcircuits (chip versions) of microcontrollers. The articles in this section discuss in some detail the basic version of the microcontrollers of the MCS-51 family (the 8051 microcircuit corresponds to the domestic analog KP1816BE51), the simplest in structural and functional terms and from the point of view of understanding.

Subsequent series of chips, while maintaining compatibility with basic version, differ from it in improved manufacturing technology, electrical parameters, additional hardware and functionality. The following articles are devoted to the structural and functional features of subsequent modifications of the MCS-51 family of microcircuits.
Generalized block diagram of MCS-51. The composition of the MC, a generalized block diagram of which is shown in Fig. 7.1.1 includes:

● 8-bit central processing unit (CPU) consisting of ALU, control devices UU and address generator F;

● mask ROM with a capacity of 4K bytes for storing programs;

● RAM with a capacity of 128 bytes for data storage;

● four programmable ports P0–P3 for input/output of information;

● serial interface unit BPI for exchanging information with external devices via a two-wire line;

● block of BT/C timers/counters to maintain real-time mode;

● BP interrupt block for organizing interruptions of executable programs. These funds form resident part of the microcontroller located directly on the chip. The MK includes a large number of registers, which are assigned to separate functional blocks and are not shown in the diagram.

The diagram also does not show control circuits. Two-way exchange of information between blocks is carried out via internal 8-bit data busШД-8.

By internal 16-bit address busША-16 The address generated in the CPU is output to ROM (12 address bits) and to RAM (8 low-order bits).

When using external memory, the 8 least significant bits of the address are output to port P0 and the 3 or 8 most significant bits to port P2.

To logically expand the interface, combining the functions of port lines is used. As an example in Fig. 7.1.1 the dotted line shows the lines of the P3 port that perform alternative functions of transmitting control signals, the purpose of which will be discussed below. To create an internal clock generator, a quartz resonator and two capacitors are connected to the terminals of the MK microcircuit (Fig. 7.1.1). Instead of an internal clock generator, an external oscillation source can be used for synchronization. The conventional graphic designation of the MK microcircuit is shown in Fig. 7.1.2, designation and purpose of pins - in table. 7.1.1. Let's consider the functional blocks of the MK and the principle of their operation. Arithmetic logic device. The arithmetic logic device is designed to perform arithmetic (including multiplication and division) and logical operations on eight-bit operands, as well as operations of logical shift, zeroing, setting, etc. The block diagram of the ALU is shown in Fig. 7.1.3.

The ALU includes

● parallel eight-bit adder SM of combinational type with sequential carry, performing arithmetic (addition and subtraction) and logical (addition, multiplication, disparity and identity) operations;

● battery A, providing the functions of the main arithmetic register;

● register B, used to implement multiplication and division operations or as an additional super-operational register, the functions of which are determined by the user;

● registers(software not available) temporary storageРВХ1, РВХ2, intended for receiving and storing operands for the duration of the operation;

● ROM constants ROM, which stores the correction code for the binary decimal representation of data, the mask code for bit operations and the code for constants;

● program status word register PSW, which records the state of the ALU after a completed operation. In table 7.1.2 provides information on the assignment of bits of individual bits of the PSW register. Control device. Control unit (CU) of the central processor intended to coordinate the joint work of all MC nodes using generated clock pulses and control signals. It consists of (Fig. 7.1.4):

● synchronization and control unit The control system, which generates clock pulses that define machine cycles and their individual states (S) and phases (P), and, depending on the operating mode of the microcontroller, generates the necessary set of control signals. It takes one, two, or four machine cycles to execute a command.

Each machine cycle has six states S1–S6, A each state includes two phases P1, P2, the duration of which is the oscillation period of the clock generator T 0SC.

The duration of the machine cycle is 12T 0SC. All machine cycles are the same, starting with phase S1P1 and ending with phase S6P2.

In addition to the clock pulses, the synchronization device generates two (sometimes one) gating signals for the low byte of the ALE address in each machine cycle in the form of a positive pulse in the phases S1P2–S2P1 and S4P2–S5P1. Timing diagrams in Fig. 7.1.5 illustrate the organization of machine cycles;

● command register RK, command decoder DC and PLM, allowing in each machine cycle to generate a set of micro-operations in accordance with the microprogram of the executed command;

● LVV input/output logic for receiving and issuing signals that ensure the exchange of information between the microcontroller and external devices through ports P0–P3;

● PCON register, which has a single enabled SMOD bit in position PCON.7 to double the serial port data rate. The remaining bits are reserved for later use.
Address generator. Address generator (FA), or PC command counter, intended to form the current 16-bit address of program memory and 8/16-bit address of external data memory. It consists of (Fig. 7.1.6):

● 16-bit buffer B, which communicates between the 8-bit SD data bus and the 16-bit internal bus (IB) of the address former;

● SI increment circuit for increasing the value of the current program memory address by one;

● register for storing the current address of PTA commands coming from the SI;

● data pointer register DPTR , consisting of two 8-bit registers DPH and DPL. It serves to store a 16-bit address of external data memory and can be used as two independent software-accessible RONs;

● register of the XRF address generator for storing the executive 16-bit address of program memory or 8/16-bit address of external data memory. This register is also used to transmit data through port P0 to external devices when executing the MOVX @Rm, A and MOVX @DPRT, A commands.

Data memory. Data memory intended for receiving, storing and issuing information used during program execution. Internal (resident) data memory (Fig. 7.1.7) consists of RAM with a capacity of 128 bytes, stack pointer S.P. address register RAM RA and decoder Dsh. The stack pointer SP is an 8-bit register designed to receive and store the address of the stack cell that was last accessed. After the reset, the stack pointer is set to address 07H, which corresponds to the beginning of the stack with address 08H. The PA address register together with the Dsh decoder allows access to the required memory cell containing a byte or bit of information.

The MK provides the ability to increase the data memory capacity up to 64 KB by connecting external storage devices. As an example in Fig. 7.1.8 shows the page organization of external VPD data memory with a capacity of 2K bytes using MOVX type commands @ Rm(m = 0; 1). In this case, port P0 operates as a multiplexed address/data bus, three lines of port P2 are used to address a page of external RAM, and the remaining five lines can be used as input/output lines.
In Fig. 7.1.9 shows timing diagrams of read and write cycles when the MK is operating with external RAM. The diagrams indicate:

● RSN - high byte of the PC command counter;

● DPL, DPH - low and high bytes of the DPTR data pointer register, which is used as a register for indirect addressing in the MOVX @DPTR,A and MOVX A,@DPTR commands;

● P2 SFR - P2 port latches;

● Rm (m = 0, 1) - registers used in the MOVX @Rm, A and MOVX A, @Rm instructions as indirect address registers;

● Z - high-resistance state;

● D - the period during which data from port P0 is entered into the microcontroller. Program memory. Program memory is designed to store programs, has its own (separate from data memory) address space and is read-only. It includes a Dsh decoder and ROM (Fig. 7.1.10). A 16-bit PC counter is used to address program memory, so its maximum capacity is 64K bytes. The internal program memory consists of a 4K byte ROM and a 12-bit decoder. External memory is connected according to the diagram in Fig. 7.1.11. If 0 V is supplied to the ¯EA pin of the MK (as shown in Fig. 7.1.11), inner memory programs are disabled. All memory accesses start at address 0000h. When the ¯EA pin is connected to a power source, access to the internal program memory at addresses 0000h–FFFFh and to the external program memory at addresses 0FFFh–FFFFh occurs automatically.

To read the external memory of MK programs, the ¯PSEN signal is generated. When working with internal memory, the read signal is not used. When accessing external program memory, a 16-bit address is always formed. The low byte of the address is transmitted through port P0 in the first half of the machine cycle and is fixed by the cut of the ALE strobe in the register. In the second half of the cycle, port P0 is used to enter a byte of data from external memory into the MK.

The most significant byte of the address is transmitted through port P2 during the entire memory access time.

Timing diagrams of read and write cycles when the MK is operating with external RAM are shown in Fig. 7.1.12.
The diagrams indicate:

● PCL OUT - output of the low byte of the PC program counter;

● RSN OUT - output of the high byte of the PC command counter;

● DPH - high byte of the DPTR data pointer register, which is used as a register for indirect addressing in the MOVX @DPTR,A and MOVX A,@DPTR instructions;

● P2 SFR - P2 port latches;

● INS IN - input of instruction (command) byte from program memory;

● ADDR OUT - issuing the low byte of the external data memory address from the Rm registers (m = 0, 1) or from the DPL register (DPTR low register). I/O ports. Port assignment. Ports P0, P1, P2, P3 intended for exchanging information between the MK and external devices, and also for performing the following functions:

● the low byte of the address A7…A0 is output through port P0; a data byte is output from the MK and entered into the MK when working with external program memory and external data memory (time-separated);

● through port P2, the high byte of the address A15...A8 is output when working with external program memory and external data memory (only when using the MOVX A,@DPTR and MOVX @DPTR,A commands);

● lines of the P3 port can be used to perform alternative functions if 1 is entered in the latch of this line, otherwise 0 is fixed at the line output. Alternative functions of the P3 port pins are given in Table. 7.1.3.

Circuit features of ports

In Fig. 7.1.13 shows diagrams for one channel of each of the MK ports, including:

● latch for fixing the received data bit;

● output amplifier cascade(driver);

● node connection with output stage (except P2);

● a circuit for transmitting a data bit from the output side of the port, consisting of buffers B2 and B3 (for port P4). The latch is a D-flip-flop, clocked by the internal “Write to latch” signal. The data bit from the direct output of the D flip-flop can be read programmatically through buffer B1 using the “Read Latch” signal to the line of the internal data bus (ID) of the MK.

Output stage port P0 is an inverter, the features of which are manifested in the fact that the load transistor VT2 opens only when accessing external memory (when transmitting addresses and data through the port). In all other modes, the load transistor is closed. Therefore, to use P0 (Fig. 7.1.13, a) as an output port general purpose external load resistors must be connected to its terminals. When writing 1 to the port latch, the inverter transistor VT1 is locked and the external pin of the P0.X port is switched to a high-resistance state. In this mode, the output of port P0.X can serve as an input. If the P0 port is used as a general purpose I/O port, each of its P0.X pins can independently operate as an input or output. Output stages ports P1, P2, P3 (Fig. 7.1.13, b, c, d) made according to inverter circuits with an internal load resistor, which is used as a transistor VT2.

To reduce the switching time when port pins transition from state 0 to state 1, an additional transistor VT3 was introduced in parallel with the load transistor VT2. Transistor VT3, using elements in the gate circuit, is unlocked for a time equal to two oscillation periods of the master quartz oscillator (during phases S1P1, S2P2 of the machine cycle). Output stages ports P0, P2 (Fig. 7.1.13, A, c) using the MX multiplexer can be connected either to latches or to the internal “Address/data” and “Address” buses. The output stage of port P1 (Fig. 7.1.13, 6) is permanently connected to the latch.

If the pin of port P3 is an output and its latch contains 1, then its output stage is controlled by the hardware internal signal “Alternate Output Function”, ensuring the execution of the corresponding alternative function, i.e. one of the signals ¯WR, ¯RD or RxD is generated at the external pin. If the port output is used as an input, then the alternative signal arriving at it (TxD, ¯INT0, ¯INT1, T0, T1) is transmitted to the “Alternative input function” internal line.

Port recording mode.

When a port write command is executed, the new value is written to the latch in phase S6P2 and output directly to the output pin of the port in phase S1P1 of the next machine cycle.

Port read mode

Read port commands read information directly from external contacts port pins or latch outputs. In the first case, the data bit from the port pin is read programmatically through buffer B2 using the “Read Pins” signal to the line of the internal data bus (SD) of the MK. Note that the signals “Write to latch”, “Read latch”, “Read pins” are generated in hardware when the corresponding commands are executed.

In the second case, the so-called “Read-Modify-Write” mode is implemented, in which the command reads the latch state signal, modifies it if necessary, and then writes it back to the latch. The “Read-Modify-Write” mode is implemented when executing the following commands: ANL, ORL, XRL, JBC; CPL; INC; DEC; DJNC; MOV PX,Y; CLR PX.Y; SETB PX,Y.

Reading information from the outputs of the latches allows you to eliminate errors when interpreting the logical level at the port pin. Read the continuation of the article.

Ministry of General and Professional Education of the Russian Federation Novosibirsk State Technical University V.N. Veprik, V.A. Afanasyev, A.I. Druzhinin, A.A. Zemskov, A.R. Isaev, O.V. Malyavko MICROCONTROLLERS OF THE MCS-51 FAMILY A textbook on the courses "Microprocessor systems" and "Design of microprocessor systems" for senior students of the Faculty of Automation and Computer Engineering of all forms of education Novosibirsk 1997 V.N. Veprik, V.A. Afanasyev, A.I. Druzhinin, A.A. Zemskov, A.R. Isaev, O.V. Malyavko. Microcontrollers of the MCS-51 family: Tutorial. - Novosibirsk. Offered to your attention contains a general description of the architecture, functionality and command system of the MCS-51 family of single-chip microcontrollers (Embedded Microcontrollers), manufactured by INTEL. The second part of the manual provides a description of the educational microprocessor controller UMPC-51, which is offered to students as an object of study when performing a cycle of laboratory work. The material in the manual can be used for course and diploma design, and can also be useful for circuit engineers involved in the development and operation of electronic equipment. also expanded due to the introduction of: two 16-bit timer-counters; hardware serial duplex port; . Features of the latest modifications of the MCS-51 family of microcontrollers are: completely static design; The third field can contain up to 15 numeric and alphabetic characters indicating the type two-level interrupt system;, located on the crystal. The fourth field can include up to six digital and alphabetic characters, reflecting various features and designs of microcircuits. microcontrollers. 1. Group 8X5X (8051 Product Line and 8052 Product Line): 8031AN, 8051AN, 8751N, 8051ANR, 8751N-8, 8751VN, 8032AN, 8052AN, 8752VN. 2. Group 8ХС51 (80С51 Product Line): 80С31ВН, 80С51ВН, 87С51. 3. Group 8ХС5Х (8ХС52/54/58 Product Line): 80С32, 80С52, 87С52, 80С54, 87С54, 80С58, 87С58. 4. Group 8ХС51FX (8XC51FA/FB/FC Product Line): 80C51FA, 83C51FA, 87C51FA, 83C51FB, 87C51FB, 83C51FC, 87C51FC. 5. Group 8ХL5X (8XL52/54/58 Product Line): 80L52, 87L52, 80L54, 87L54, 80L58, 87L58. 6. Group 8XL51FX (8XL51FA/FB/FC Product Line): 80L51FA, 83L51FA, 87L51FA, 83L51FB, 87L51FB, 83L51FC, 87L51FC. 7. Group 8ХС51RX (8XC51RA/RB/RC Product Line): 80C51RA, 83C51RA, 87C51RA, 83C51RB, 87C51RB, 83C51RC, 87C51RC. 8. Group 8ХC51GB (8XC51GX Product Line): 80C51GB, 83C51GB, 87C51GB. 9. Group 8ХС152JX (8XC152 Product Line): 80C152JA, 83C152JA, 80C152JB, 80C152JC, 83C152JC, 80C152JD. 10. Group 8XC51SL (8XC51SL Product Line): 80C51SL-BG, 81C51SL-BG, 83C51SL-BG, 80C51-AH, 81C51SL-AH, 83C51SL-AH, 87C51SL-AH, 80C51SL-AL, 81C51SL-AL, AL, 87C51SL-AL. The first group of microcontrollers includes low-end models of the family, made using n-MOS technology and not recommended for use in new developments; all other groups are made using modern CMOS technology. Microcircuits of the second, third and fourth groups are today classic representatives of the MCS-51 family. The fifth and sixth groups include 3-volt versions of crystals (Low-Voltage). Crystals of the seventh group are equipped with expanded RAM (Expanded RAM), the volume of which is 512 bytes. Microcircuits of the eighth, ninth and tenth groups are application-specific microcontrollers (Application Specific). Many modern applications require high-performance control microcontrollers that use advanced addressing capabilities, register architecture, large amounts of internal RAM and stack, and effectively support programming in the language high level microcontroller MCS-51/MCS-251 are given in the appendix. 6 2. MAIN CHARACTERISTICS OF THE BASIC MODEL OF THE MCS-51 FAMILY OF MICROCONTROLLERS. The basic model of the MCS-51 microcontroller family and the basis for all subsequent modifications is the I-8051 microcontroller. Its main characteristics are as follows: an eight-bit CPU optimized for control functions; built-in clock generator; . The MCS-51 instruction set contains a wide selection of bit operations, and the 128 bits in this block are directly addressable and have addresses ranging from 00H to 7FH.

At the origins of the production of microcontrollers is Intel with the families of eight-bit microcontrollers 8048 and 8051. The MCS-51 architecture takes its name from the first representative of this family - the 8051 microcontroller, released in 1980 based on HMOS technology. A successful set of peripheral devices, the ability to flexibly select external or internal program memory, and an affordable price ensured this microcontroller's success in the market. From a technology point of view, the 8051 microcontroller was a very complex product for its time - 128 thousand transistors were used in the crystal, which was 4 times the number of transistors in the 16-bit 8086 microprocessor.

The main elements of the basic architecture are:
- 8-bit ALU based on battery architecture;
- 4 banks of registers, 8 in each;
- built-in program memory 4KB;
- internal RAM 128 bytes;
- Boolean processor
-2 sixteen-bit timers;
- serial channel controller (UART);
- interrupt processing controller with two priority levels;
- four 8-bit I/O ports, two of which are used as an address/data bus for accessing external program and data memory;
- built-in clock generator.

It is this microcontroller that is most well known to developers and is a popular control tool in a wide range of devices. There are many emulators, debuggers and 8051 chip programmers available, so software development is a breeze.

The next fundamental step in the development of the MCS-51 was the transfer of manufacturing technology to CHMOS. This made it possible to implement Idle and Power Down modes, which dramatically reduced the power consumption of the crystal and paved the way for the use of the microcontroller in energy-dependent applications, for example, in stand-alone battery-powered devices.

And the last fundamental stage in the development of this direction by Intel within the framework of 8-bit architecture was the release of microcontrollers 8xC51FA/FB/FC, which for brevity are often referred to as 8xC51FX. The main distinguishing feature of this group of crystals is the presence of a programmable counter array (PCA). The PCA block diagram is shown in Fig. 2.

The PCA includes:

The timer-counter serves all five sampling and comparison modules, which can be programmed to perform one of the following functions:

	16-bit sampling of the timer value on the positive edge of an external signal;
	16-bit sampling of the timer value on the negative edge of an external signal;
	16-bit sampling of the timer value on any edge of an external signal;
	16-bit software timer;
	16-bit High Speed ​​Output (HSO);
	8-bit PWM

All of the above functions are performed in the PCA at the hardware level and do not load the central processor, which allows increasing the overall system throughput, increasing the accuracy of measurements and signal processing, and reducing the microcontroller’s response time to external events, which is especially important for real-time systems. The PCA implemented in 8xC51FX turned out to be so successful that the FX microcontroller architecture became a de facto industry standard, and the PCA itself was reproduced many times in various modifications of microcontrollers from different companies.

Initially, the biggest bottlenecks of the MCS-51 architecture were the 8-bit battery-based ALU and relatively slow instruction execution (the fastest instructions require 12 clock cycles to execute). This limited the use of microcontrollers of the family in applications requiring increased speed and complex calculations (16- and 32-bit). The issue of fundamental modernization of the old architecture became urgent. The problem of modernization was complicated by the fact that by the beginning of the 90s a lot of developments in the field of software and hardware had already been created, and one of the main tasks of developing a new architecture was to implement hardware and software compatibility with older developments based on the MCS-51. To solve this problem, a joint group of specialists from Intel and Philips was created. As a result, in 1995, 2 significantly different families appeared: MCS-251/151 from Intel and 51XA from Philips (we will discuss the latter below).

Main characteristics of the MSC-251 architecture:

	24-bit linear address space addressing up to 16M memory(manufactured microcontrollers of the MCS-251 family have a memory address space of 256K);
	The command system of the MCS-251 family of microcontrollers contains all 111 commands included in the command system of the MCS-51 family of microcontrollers (“old” commands), and, in addition, it includes 157 “new” commands. Some new command codes are in 4 byte format.
	Before using the microcontroller, it must be configured, i.e. using the programmer, “burn” the configuration bytes that determine which of the instruction sets will become active after turning on the power. If you install the MCS-51 instruction set, then the MSC-251 will be compatible with the MCS-51 at the binary code level. This mode is called Binary Mode. However, extended instructions in this mode are also available through a "window" - the reserved instruction code 0A5h. Naturally, the length of each extended instruction increases in this case by 1 byte. If you initially install a set of extended instructions, then in this case programs written for MCS-51 will require recompilation using cross-tools for MCS-51, because

	now standard instructions will be available through the same “window” 0A5h and their length will also increase by 1 byte. This mode is called Source Mode. It allows you to use extended instructions with maximum efficiency and achieve the highest performance, but requires software rework.
	register architecture, allowing registers to be accessed as bytes, words, and double words;
	page addressing mode to speed up fetching instructions from external program memory;
	instruction queue;
	extended instruction set, including 16-bit arithmetic and logical instructions;
	expanded stack address space up to 64K;
	execution of the fastest instruction in 2 clock cycles;

Binary compatibility with programs for MCS-51.

For users focused on using MCS-251 microcontrollers as a mechanical replacement for MCS-51, Intel produces MCS-251 microcontrollers with already programmed configuration bits in the Binary Mode state. Such microcontrollers received the MCS-151 index.

In addition to Intel itself, Temic Semiconductors produces MCS-251 microcontrollers under its license. Universal serial bus

In order to provide the ability to connect a variety of peripheral devices, the USB standard defines four transfer modes: Control, Isochronous, Pulse, and Array Transfer. Each peripheral device must support a control mode to transfer configuration parameters, commands, and device status information. Isochronous transmission provides guaranteed bus access, constant throughput, and error tolerance, and can be used in audio output devices and computer telephony applications. Pulse transmission is intended for input devices such as a mouse, joystick or keyboard that transmit information infrequently and in small portions, but with a limited service period. Bulk transfer allows devices such as scanners, fax machines, or digital cameras to transfer large amounts of data to a personal computer as soon as a bus channel becomes available.

Main Product Features

Fully compatible with the "Universal Serial Bus Specification 1.0" Built-in USB transceiver Serial Bus Interface Engine (SIE) Four FIFO queues for transmission Three 16-byte FIFO queues Four FIFO receive queues Three 16-byte FIFO queues One configurable FIFO queue (up to 1024 bytes) Automatic transmit/receive control in FIFO queues Stop/Resume Operations Three USB Bus Interrupt Vectors Phase lock cycle Data transfer rates: 12 Mbit/s and 1.5 Mbit/s Slow Cycle Mode 256 KB external address space Energy saving modes: standby and power off User Defined Parameters Real time waiting 1 KB random access memory on chip
	Four I/O ports
	Programmable Counter Array (PCA)
	Standard (MCS 51) UART microcontroller
	Hardware watchdog timer
	Three 16-bit timers/counters with flexible capabilities
	Compatible with MCS 51 and MCS 251 architecture microcontroller instruction set
	MCS 251 microcontroller architecture based on registers
	Operating frequency 6 or 12 MHz

The 8x930Hx controller has additional features:

	USB hub
	USB hub control options Connection management Connection/disconnection detection with output device Power management including stop/resume Bus fault detection and recovery Supports full-speed and low-speed output devices
	Output contact for switching port power
	Input contact for overload detection

The four different modes of USB data transfer are provided by the collaboration of three elements: Host, Hub, Functional Device. The host controls the transmission of content and control information via the bus. Functional devices extend host systems. This includes typical types of work with a PC: input from a keyboard or joystick, output to a monitor; as well as more complex activities such as digital telephony and image transmission. An Intel 8x930Ax microcontroller was designed to control functional devices. Finally, hubs provide a USB expansion point that provides access to other functional devices. The Intel 8x930Hx microcontroller, which combines functional device and USB hub control functions, is the first commercially available USB hub designed for modern PC peripherals.

USB hubs play a significant role in expanding the world of PC users. With the advent of peripherals - keyboards, monitors, printers and others - equipped with built-in hubs, connecting or unplugging a new device is as easy as plugging it into an outlet. New levels of performance and expanded USB connectivity could lead to a new generation of devices for work and entertainment applications. The days of embedded cards, IRQ conflicts, and tangled tangles of wires are numbered.

The USB bus cable consists of only four wires: Vbus, D+, D- and GND - which makes the connection simpler and more uniform. A single standard connector for connecting peripheral devices to the USB bus serves the same purpose. Data is transferred differently on D+ and D- cables: either at full speed of 12 Mbps, or at low speed of 1.5 Mbps. The transceiver is built into the chip, so there is no need for external electronic circuits. The exception is the terminal load resistor on both the D+ and D- lines, which is necessary to determine whether the device is high-speed or low-speed.

Family overview
The Intel 8x930 family consists of two single-chip controllers.

The Intel 8x930Ax controller is an 8-bit device that is based on the MCS 251 microcontroller architecture and is designed to work with peripheral devices connected to the USB bus. On the other hand, the 8x930Hx uses the same MCS 251 microcontroller core plus the enhanced capabilities of the built-in USB bus hub. The use of the MCS 251 architecture in both USB bus controllers provides the following advantages:

	High performance
	Application of mixed types of memory and addressing
	Low power consumption
	Low noise level
	Effective support for high-level languages
	Extended command set
	Built-in capabilities

The 8x930Ax can use instructions from both the MCS 51 Microcontroller Set and the MCS 251 Microcontroller Set. This approach preserves the user's investment in software and squeezes maximum performance out of applications.

The 8x930 microcontrollers are so rich in various built-in features that they look more powerful than just microcontrollers. The Programmable Counter Array (PCA) provides flexibility for applications that require real-time data comparison or capture, high-speed communications, or pulse-width modulation. In addition, the controller includes an extended serial port, three 16-bit timers/counters, a hardware watchdog, four 8-bit I/O ports, and two power-saving modes: sleep and power off.

The 8x930Ax family of controllers are equipped with 1 KB of memory and can be used in versions without persistent memory, or with 8 or 16 KB of persistent memory. They can address up to 256 KB of external memory for instructions and data and 40 bytes of general purpose registers, which are located in the central processor as a register file. Depending on the combination used, the register file may contain 16 byte registers, 16 two-byte registers, and 10 four-byte registers.

The controllers provide a flexible interface with external memory. To access devices with slow memory, it is possible to add three wait cycles, and to generate more cycles, a call to the real-time function is possible. Fetching external instructions can improve performance by using paging mode, which shuffles data in the high byte of the address.

Both 8x930 controllers feature eight FIFO queues to support internal devices output: four queues for transmission and four queues for reception. Four transmit/receive FIFO queues support four end functional units (0 to 3). Queue 0 consists of 16 bytes and is intended for transmitting control information. Queue 1 is user configurable and has a capacity of up to 1024 bytes. Queues 2 and 3 consist of 16 bytes each and can be used to transmit information in burst, isochronous, and array modes. When using an 8x930Hx controller, these queues are reinforced by a pair of FIFO queues for input devices. These queues in the 8x930Hx controller are supported by an additional repeater, which is responsible for retransmitting the data streams generated by the output devices.

Architecture overview
Structurally, the implementation of USB in the 8x930Ax and 8x930Hx microcontrollers can be divided into four blocks: FIFO queues, an interface block with functional devices, a serial bus interface block, and a transceiver. The 8x930Hx controller has additional blocks to control the functions of the hub: a hub interface block and a repeater.

The receive and transmit FIFO queues on both controllers are circular. Queues support up to two separate data sets of variable size and contain byte counter registers that indicate the number of bytes in the data sets. Queues have flags indicating whether the queue is full or empty, and can also repeat the reception or transmission of the current set of data. The Functional Unit Interface Unit (FUI) distributes transmitted or received USB data according to the type of transmission and the state of the queues. In addition, the FFU block monitors the transaction status, manages FIFO queues, and, using an interrupt request, reports the occurrence of control events to the 8x930 central processor.

The serial bus interface block implements the USB transmission protocol: sequentially arranges packets, generates and recognizes a signal, generates and verifies checksums, encodes/decodes data using the NRZI method, bit stuffing, generates and recognizes a packet identifier (PID).

The integrated transceiver on USB microcontrollers is compatible with a simple four-wire interface defined by the USB 1.0 specification. The 8x930 family of controllers has three USB-related interrupts. They occur at each start of a frame, the end of receiving/transmitting data to terminal functional devices, in the event of a global suspension or resumption of work. In the 8x930Hx hub, the hub interface unit is used to control and monitor the connection status of the output ports. The repeater is responsible for distributing the up and down signals from the USB ports.

LECTURE PLAN

1. Introduction

2. Arithmetic and logical instructions

3. Data transfer commands

4. Boolean operations

5. Jump instructions

1. Introduction

Command system MCS-51 supports a single set of instructions, which is designed to execute 8-bit actuator control algorithms. It is possible to use quick methods addressing internal RAM, performing bit operations on small data structures. There is an extensive system for addressing single-bit variables as an independent data type, which allows the use of individual bits in logical and control commands of Boolean algebra.

Addressing modes : command set MCS-51 supports the following addressing modes. Direct addressing: The operand is determined by the 8-bit address in the instruction. Direct addressing is used only for the low half of the internal data memory and registers SFR. Indirect addressing: The instruction addresses a register containing the address of the operand. This type addressing is used for external and internal RAM. Registers can be used to specify 8-bit addresses R0 And R1 selected register bank or stack pointer SP. For 16-bit addressing, only the data pointer register is used DPTR.

Register instructions : registers R0–R7 current register bank can be addressed via specific instructions containing a 3-bit field indicating the register number in the instruction itself. In this case, the corresponding address field is missing from the command. Operations using special registers: some instructions use individual registers (for example, accumulator operations, DPTR, etc.). In this case, the operand address is not specified in the command at all. It is predetermined by the operation code.

Immediate constants : the constant can be located directly in the command after the opcode.

Index addressing : Index addressing can only be used to access program memory and only in read mode. In this mode, tables in program memory are viewed. 16-bit register ( DPTR or program counter) indicates the base address of the desired table, and the accumulator indicates the entry point into it.

Command sethas 42 command mnemonics to specify the 33 functions of this system. The syntax of most assembly language instructions consists of a function mnemonic followed by operands indicating addressing methods and data types. Different data types or addressing modes are determined by the set operands, not by changes in mnemonics.

The command system can be divided into five groups: arithmetic commands; logical commands; data transfer commands; bit processor commands; branching and control transfer commands. The notations and symbols used in the command system are given below.

Table. Notations and symbols used in the command system

Designation, symbol	Purpose
	Battery
	Registers of the currently selected register bank
	The number of the loaded register specified in the command
direct	Directly addressable 8-bit internal data cell address, which can be an internal data RAM cell (0–127) or an SFR special function register (128–255)
	Indirectly addressable 8-bit internal data RAM cell
	8-bit direct data included in the operation code (OPC)
dataH	Most significant bits (15–8) of the immediate 16-bit data
dataL	Least significant bits (7–0) of immediate 16-bit data
	11-bit destination address
addrL	Least significant bits of destination address
	8-bit signed offset byte
	Directly addressable bit whose address contains the COP located in the internal data RAM or special function register SFR
a15, a14...a0	Destination address bits
	Contents of element X
	Contents at the address stored in element X
	Bit M of element X
+ – * AND OR XOR /X	Operations: addition subtraction multiplication divisions logical multiplication (AND operation) logical addition (OR operation) addition modulo 2 (exclusive OR) inversion of element X

Function mnemonics are uniquely associated with specific combinations of addressing methods and data types. In total, there are 111 such combinations possible in the command system.

2. Arithmetic and logical instructions

How p example arithmetic instruction, the addition operation can be performed by one of the following commands.

ADDA,7 F 16 – add the number 7 to the contents of register A F 16 and store the result in register A;

ADDA,@ R0 – add to the contents of register A the number whose address (@ – commercial at ) is stored in a register R 0 (indirect addressing), and store the result in register A;

ADD A,R7– add the contents of register A to the contents of register R 7 and save the result in register A;

ADD A,#127– add to the contents of register A a number whose storage cell address is 127 ( # – number symbol), and save the result in the registry T- re A.

All arithmetic instructions are executed in one machine cycle with the exception of the instruction INC DPTR(data pointer offset DPTR to the next byte), requiring two machine cycles, as well as multiplication and division operations performed in 4 machine cycles. Any byte in the internal data memory can be incremented and decremented without using a battery.

Instructions MUL AB performs multiplication (multiplication) of the data in the accumulator by the data in register B, placing the product in registers A (low half) and B (high half).

Instructions DIV AB divides (division) the contents of the accumulator by the value in register B, leaving the remainder in B and the quotient in the accumulator.

Instructions DA A is intended for binary decimal arithmetic operations (arithmetic operations on numbers represented in binary decimal code). She doesn't do the conversion binary number V BCD, but only provides the correct result when adding two binary decimal numbers.

Example logical command: A logical AND operation can be performed by one of the following commands:

ANLA,7 F 16 – logical multiplication of the contents of register A by the number 7 F 16 and the result is stored in register A;

ANLA,@ R1 – logical multiplication of the contents of register A by the number whose address is stored in the register R 1 (indirect addressing), and store the result in register A;

ANL A,R6– logical multiplication of the contents of register A by the contents of the register R 6, and save the result in register A;

ANL A,#53 – logical multiplication of the contents of register A by a number whose storage cell address is 53 16, and the result is stored in register A.

All logical operations on the contents of the accumulator are performed in one machine cycle, the rest - in two. Logical operations can be performed on any of the lower 128 bytes of internal data memory or on any register SFR (special function registers) in direct addressing mode without using a battery.

The rotary shift operations RL A, RLC A, etc. move the contents of the accumulator one bit to the right or left. In the case of a left cyclic shift, the least significant bit is moved to the most significant position. In the case of a right cyclic shift, the opposite occurs.

Operation SWAP A exchanges the low and high tetrads in the battery.

3. Data transfer commands

Team MOV dest,src allows you to transfer data between internal RAM cells or special function register areas SFR without using a battery. In this case, work with the upper half of the internal RAM can only be carried out in indirect addressing mode, and access to registers SFR– only in direct addressing mode.

In all microcircuits MCS-51 The stack is placed directly in the resident data memory and grows upward. Instructions PUSH first increments the value in the stack pointer register SP, and then writes a byte of data onto the stack. Teams PUSH And POP are used only in direct addressing mode (writing or restoring a byte), but the stack is always accessible when indirectly addressing via a register SP. Thus, the stack can also use the top 128 bytes of data memory. The same considerations exclude the possibility of using stack instructions to address registers SFR.

Data transfer instructions include a 16-bit transfer operation MOV DPTR,#data16, which is used to initialize the data pointer register DPTR when viewing tables in program memory or to access external data memory.

Operation XCH A,byte used to exchange data between the accumulator and the addressed byte. Team XCHD A,@Ri similar to the previous one, but is performed only for the lower tetrads involved in the exchange of operands.

To access external data memory, only indirect addressing is used. In the case of single-byte addresses, registers are used R0 or R1 current register bank, and for 16-bit – data pointer register DPTR. With any method of accessing external data memory, the battery plays the role of a source or receiver of information.

To access tables located in program memory, use the following commands:

MOVC A,@A+ DPTR ;

MOVC A,@A+ PC .

The contents of the data pointer register are used as the base address of the table DPTR or PC(program counter), and the offset is taken from A. These instructions are used exclusively to read data from program memory, but not to write to it.

4. Boolean operations

Microcircuits MCS-51 contain a “Boolean” processor. The internal RAM has 128 directly addressable bits. Special function register space SFR can also support up to 128 bit fields. Bit instructions perform conditional branches, transfers, resets, inversions, AND and OR operations. All specified bits are available in direct addressing mode.

Carry bit CF in the special function register “program status word” P.S.W." is used as a one-bit accumulator for a Boolean processor.

5. Jump instructions

The addresses of jump operations are indicated in assembly language by a label or by a real value in program memory space. Conditional branch addresses are assembled into a relative offset - a sign byte added to the program counter PC if the transition condition is met. The boundaries of such transitions lie between minus 128 and 127 relative to the first byte following the instruction. In the special function register "program status word" P.S.W." there is no zero flag, so the instructions JZ And JNZ check the condition “equal to zero” as testing the data in the accumulator.

There are three types of unconditional jump command: SJMP, LJMP And AJMP– destination addresses that differ in format. Instructions SJMP encodes the address as a relative offset, and takes two bytes. The jump distance is limited to the range from minus 128 to 127 bytes relative to the instruction following SJMP.

In the instructions LJMP The destination address is used as a 16-bit constant. The command length is three bytes. The destination address can be located anywhere in program memory.

Team AJMP uses an 11-bit address constant. The command consists of two bytes. When this instruction is executed, the lower 11 bits of the address counter are replaced by the 11-bit address from the instruction. The five most significant bits of the program counter PC remain unchanged. Thus, the transition can be made within a 2K-byte block in which the instruction following the instruction is located AJMP.

There are two types of command calls to a subroutine: LCALL And ACALL. Instructions LCALL uses the 16-bit address of the called subroutine. In this case, the subroutine can be located anywhere in the program memory. Instructions ACALL uses an 11-bit subroutine address. In this case, the called routine must be located in a single 2K byte block with the instruction following ACALL. Both versions of the instruction push the address of the next instruction onto the stack and load it into the program counter PC corresponding new value.

The subroutine ends with the instruction RET, which allows you to return to the instruction following the command CALL. This instruction pops the return address off the stack and loads it into the program counter. PC . Instructions RETI used to return from interrupt routines. The only difference RETI from RET is that RETI informs the system that interrupt processing has completed. If at the time of execution RETI there are no other interrupts, then it is identical RET.

Instructions DJNZ designed to control cycles. To execute a loop N once you need to load a byte with a value into the counter N and close the loop body with the command DJNZ, indicating the beginning of the cycle.

Team CJNE compares its two operands as unsigned integers and jumps to the address specified therein if the operands being compared are not equal. If the first operand is less than the second, then the carry bit CF is set to "1".

All instructions in assembled form occupy 1, 2 or 3 bytes.

ARCHITECTURE OF MICROCONTROLLER FAMILYMCS-51

Lecture notes for courses

“Microprocessors in control systems”, “Microprocessor technology”

"Microprocessor tools and systems"

for students of all forms of study specialties

072000 – Standardization and certification

210200 – Automation of technological processes

230104 – Computer-aided design systems

Tambov 2005

INTRODUCTION.. 3

1. STRUCTURE OF THE INTEL 8051 MICROCONTROLLER. 3

1.1. Organization of memory. 5

1.2. Arithmetic-logical device. 6

1.3. Resident memory for programs and data. 7

1.4. Accumulator and general purpose registers. 8

1.5. The program status word register and its flags. 9

1.6. Pointer registers. 10

1.7. Special function registers. eleven

1.8. Control and synchronization device. eleven

1.9. Parallel information input/output ports. 12

1.10. Timers/counters. 13

1.11. Serial port. 18

1.11.1. Register SBUF.. 18

1.11.2. Serial port operating modes. 18

1.11.3. Register SCON.. 19

1.11.4. Reception/transmission speed. 21

1.12. Interrupt system. 22

2. COMMAND SYSTEM OF THE INTEL 8051 MICROCONTROLLER. 26

2.1. General information. 26

2.1.1. Types of commands. 27

2.1.2. Operand types. 28

2.1.3. Data addressing methods. thirty

2.1.4. Result flags. 31

2.1.5. Symbolic addressing. 32

2.2. Data transfer commands. 33

2.2.1. Structure of information links. 33

2.2.2. Accessing the battery. 33

2.2.3. Accessing external data memory. 34

2.2.4. Accessing program memory... 34

2.2.5. Access to the stack. 35

2.3. Arithmetic operations. 35

2.4. Logical operations. 39

2.5. Control transfer commands. 43

2.5.1. Long transition. 43

2.5.2. Absolute transition. 43

2.5.3. Relative transition. 44

2.5.4. Indirect transfer. 44

2.5.5. Conditional jumps.. 44

2.5.6. Subroutines.. 47

2.6. Operations with bits. 48

Test questions... 49

LITERATURE.. 50

Appendix INTEL 8051 COMMAND SYSTEM. 51

INTRODUCTION

Since the 80s of the 20th century, an independent class of integrated circuits has emerged in microprocessor technology - single-chip microcontrollers, which are designed for integration into devices for various purposes. They are distinguished from the class of single-chip microprocessors by the presence of internal memory and developed means of interaction with external devices.

8-bit single-chip microcontrollers of the MCS-51 family are widely used. This family was formed on the basis of the Intel 8051 microcontroller, which has gained great popularity among developers of microprocessor control systems due to its well-designed architecture. The microcontroller architecture is a set of internal and external software-accessible hardware resources and command systems.

Subsequently, Intel released about 50 models based on the operating core of the Intel 8051 microcontroller. At the same time, many other companies, such as Atmel, Philips, began producing their own microcontrollers developed in the MCS-51 standard. There is also a domestic analogue of the Intel 8051 microcontroller - the K1816BE51 chip.

2. STRUCTURE OF THE INTEL 8051 MICROCONTROLLER

The Intel 8051 microcontroller is based on high-level n-MOS technology. Its main characteristics are as follows:

· eight-bit central processor optimized for implementation of control functions;

· built-in clock generator (maximum frequency 12 MHz);

· program memory address space - 64 KB;

· data memory address space - 64 KB;

· internal program memory - 4 KB;

· internal data memory - 128 bytes;

· additional capabilities for performing Boolean algebra operations (bitwise operations);

· 2 sixteen-bit multifunctional timers/counters;

· full-duplex asynchronous transceiver (serial port);

· vectored interrupt system with two priority levels and five event sources.

Figure 1 - Block diagram of the Intel 8051 microcontroller

The basis of the block diagram (Fig. 1) is formed by an internal bidirectional 8-bit bus, which interconnects the main nodes and devices of the microcontroller: resident program memory (RPM), resident data memory (RDM), arithmetic-logical unit (ALU), register unit special functions, control unit (CU), parallel I/O ports (P0-P3), as well as programmable timers and a serial port.

2.1. Memory organization

This microcontroller has a built-in (resident) and external memory programs and data. The resident program memory (RPM) has a capacity of 4 KB, and the resident data memory (RDM) has a capacity of 128 Bytes.

Depending on the modification of the microcontroller, RPM is implemented in the form of a mask ROM, one-time programmable or reprogrammable ROM.

If necessary, the user can expand the program memory by installing an external ROM. Access to internal or external ROM is determined by the value of the signal at pin EA (External Access):

EA=VCC (supply voltage) - access to internal ROM;

EA=VSS (ground potential) - access to external ROM.

External program and data memory can be 64 KB each and addressed using ports P0 and P2. Figure 2 shows the Intel 8051 memory card.

Figure 2 - Intel 8051 memory organization

External ROM read strobe - (Program Store Enable) is generated when accessing external program memory and is inactive while accessing the ROM located on the chip.

The area of ​​lower program memory addresses (Fig. 3) is used by the interrupt system. The INTEL 8051 chip architecture provides support for five interrupt sources. The addresses to which interrupt control is transferred are called interrupt vectors.

Figure 3 - Map of the lower program memory area

2.2. Arithmetic logic unit

The 8-bit arithmetic logic unit (ALU) can perform the arithmetic operations of addition, subtraction, multiplication, and division; logical operations AND, OR, exclusive OR, as well as operations of cyclic shift, reset, inversion, etc. Software-inaccessible registers T1 and T2, intended for temporary storage of operands, a decimal correction circuit (DCU) and a feature generation circuit are connected to the inputs operation result (PSW).

The simple addition operation is used in the ALU to increment the contents of registers, advance the data pointer register (RAR), and automatically calculate the next program resident memory address. The simplest subtraction operation is used in the ALU to decrement registers and compare variables.

The simplest operations automatically form “tandems” to perform operations such as, for example, incrementing 16-bit register pairs. The ALU implements a mechanism for cascading execution of simple operations to implement complex commands. So, for example, when executing one of the conditional control transfer commands, based on the comparison result in the ALU, the program counter (PC) is incremented three times, the RDM is read twice, an arithmetic comparison of two variables is performed, a 16-bit transition address is formed, and a decision is made on whether to or not make the transition according to the program. All of the above operations are performed in just 2 μs.

An important feature of the ALU is its ability to operate not only bytes, but also bits. Individual software-accessible bits can be set, cleared, inverted, transmitted, tested, and used in logical operations. This ability is quite important, since to control objects, algorithms are often used that contain operations on input and output Boolean variables, the implementation of which is associated with certain difficulties using conventional microprocessors.

Thus, the ALU can operate with four types of information objects: Boolean (1 bit), digital (4 bits), byte (8 bits) and address (16 bits). The ALU performs 51 different operations to forward or transform this data. Since there are 11 addressing modes (7 for data and 4 for addresses), by combining the operation and addressing mode, the basic number of 111 instructions is expanded to 255 out of 256 possible with a single-byte opcode.

2.3. Resident program and data memory

Residential (on-chip) program memory (RPM) and data memory (RDM) are physically and logically separated, have different addressing mechanisms, operate under different signals, and perform different functions.

The RPM program memory has a capacity of 4 KB and is designed to store commands, constants, initialization control words, conversion tables for input and output variables, etc. The memory has a 16-bit address bus, through which access is provided from the PC program counter or from the register. data pointer (DPTR). DPTR functions as a base register for indirect program jumps or is used in table operations.

The RDM data memory is designed to store variables during execution of an application program, is addressable by one byte and has a capacity
128 bytes. In addition, its address space is adjacent to the addresses of special function registers, which are listed in Table. 1.

The program memory, like the data memory, can be expanded to
64 KB by connecting external chips.

Table 1

Special function register block

	Name
		Battery
		Accumulator expander register
		Program status word
		Stack pointer register
		Data pointer register
		Interrupt Priority Register
		Interrupt Mask Register
		Timer/Counter Mode Register
		Timer Control/Status Register
		Timer 0 (high byte)
		Timer 0 (low byte)
		Timer 1 (high byte)
		Timer 1 (low byte)
		Transceiver Control Register
		Transceiver Buffer
		Power control register

Note. Registers whose names are marked with (*) allow individual bits to be addressed.

2.4. Accumulator and general registers

The accumulator (A) is the source of the operand and the location of the result when performing arithmetic, logical operations and a number of data transfer operations. In addition, shift operations, checking for zero, generating a parity flag, etc. can only be performed using the accumulator.

The user has four banks of 8 general purpose registers R0–R7 at his disposal (Fig. 9). However, it is possible to use the registers of only one of the four banks, which is selected using the PSW register bit.

2.5. Program status word register and its flags

When many instructions are executed in the ALU, a number of operation attributes (flags) are generated, which are recorded in the program status word (PSW) register. In table 2 provides a list of PSW flags, gives their symbolic names and describes the conditions for their formation.

table 2

PSW Program Status Word Format

		Name and purpose
		Carry flag. Set and reset by hardware or software when performing arithmetic and logical operations
		Auxiliary carry flag. Set and cleared only by hardware when adding and subtracting instructions are executed and signals a carry or borrow in bit 3
		Flag 0. Can be set, cleared, or checked by the program as a user-specified flag.
		Selecting a register bank. Set and reset by software to select a working bank of registers (Table 3)
		Overflow flag. Set and reset by hardware when performing arithmetic operations
		Not used
		Parity flag. Set and reset by hardware in each cycle and fixes the odd/even number of one bits in the accumulator, i.e. performs parity

Table 3

Selecting a working register bank

			Address Boundaries

The most “active” PSW flag is the carry flag, which is involved and modified during many operations, including addition, subtraction and shifts. In addition, the carry flag (CY) functions as a “Boolean accumulator” in bit-manipulating instructions. The overflow flag (OV) detects arithmetic overflow in signed integer operations and makes it possible to use arithmetic in two's complement codes. The ALU does not control the register bank selection flags (RS0, RS1), their value is completely determined by the application program and is used to select one of the four register banks.

As a byte, the PSW register can be represented as follows:

In microprocessors whose architecture relies on an accumulator, most instructions operate on the accumulator using implicit addressing. The Intel 8051 is different. Although the processor is based on a battery, it can execute many commands without its participation. For example, data can be transferred from any RDM cell to any register, any register can be loaded with an immediate operand, etc. Many logical operations can be performed without involving an accumulator. Additionally, variables can be incremented, decremented, and checked without using an accumulator. Flags and control bits can be checked and changed in the same way.

2.6. Pointer registers

The 8-bit stack pointer (SP) can address any RDM area. Its contents are incremented before the data is stored on the stack during PUSH and CALL instructions. The contents of the SP are decremented after the POP and RET commands are executed. This method of addressing stack elements is called pre-increment/post-decrement. During the initialization of the microcontroller, after the RST signal, code 07H is automatically loaded into the SP. This means that if application program does not override the stack, then the first data element in the stack will be located in the RDM cell with address 08H.

The two-byte data pointer register DPTR is typically used to capture a 16-bit address in external memory access operations. By microcontroller commands, the data pointer register can be used either as a 16-bit register or as two independent 8-bit registers (DPH and DPL).

2.7. Special function registers

Registers with symbolic names IP, IE, TMOD, TCON, SCON and PCON are used to capture and program change control bits and status bits for interrupt circuitry, timer/counter, serial port transceiver, and for power management. Their organization will be described in detail in sections 1.8-1.12, when considering the features of the microcontroller in various modes.

2.8. Control and synchronization device

A quartz resonator connected to the external pins of the microcontroller controls the operation of the internal oscillator, which in turn generates synchronization signals. The control unit (CU), based on synchronization signals, generates a machine cycle of a fixed duration equal to 12 generator periods. Most microcontroller instructions are executed in one machine cycle. Some instructions that operate on 2-byte words or access external memory take two machine cycles to complete. Only the division and multiplication instructions require four machine cycles. Based on these operating features of the control device, the execution time of application programs is calculated.

In the microcontroller circuit, an instruction register (IR) is adjacent to the control device. Its function is to store the code of the command being executed.

Input and output signals of the control and synchronization device:

1. PSEN – program memory resolution,

2. ALE – address fixation enable output signal,

3. PROG – programming signal,

4. EA – blocking work with internal memory,

5. VPP – programming voltage,

6. RST – general reset signal,

7. VPD – output backup power memory from an external source,

8. XTAL – inputs for connecting a quartz resonator.

2.9. Parallel input/output ports

All four ports (P0-P3) are designed to input or output information byte by byte. Each port contains a controlled latch register, an input buffer and an output driver.

The output drivers of ports P0 and P2, as well as the input buffer of port P0, are used when accessing external memory. In this case, through port P0 in time multiplexing mode, the low byte of the address is first output, and then the data byte is issued or received. Port P2 outputs the most significant byte of the address in cases where the address width is 16 bits.

All pins of port P3 can be used to implement the alternative functions listed in table. 4. These functions can be enabled by writing 1 to the corresponding bits of the latch register (P3.0-P3.7) of port P3.

Table 4

Alternative P3 Port Functions

		Name and purpose
		Reading. Active signal low level generated in hardware when accessing external data memory
		Record. An active low-level signal is generated by hardware when accessing external data memory
		Timer/counter input 1 or test input
		Timer/counter input 0 or test input
		Interrupt request input 1. Senses low level or cutoff signal
		Interrupt request input 0. Senses low level or cutoff signal
		Serial port transmitter output in UART mode. Clock output in shift register mode
		Serial port receiver input in UART mode. Data input/output in shift register mode

Port 0 is bidirectional and ports 1-3 are quasi-bidirectional. Each port line can be used independently for input or output.

Based on the RST signal, units are automatically written to the latching registers of all ports, thereby setting them up for input mode.

All ports can be used to organize information input/output via bidirectional transmission lines. However, ports P0 and P2 cannot be used for this purpose if the system has external memory, communication with which is organized through a common shared address/data bus operating in time multiplexing mode.

Accessing I/O ports is possible using commands that operate on a byte, an individual bit, or an arbitrary combination of bits. Moreover, in cases where the port is both an operand and the destination of the result, the control device automatically implements a special mode called “read-modify-write”. This mode of operation involves input of signals not from external terminals port, and from its latch register, which eliminates incorrect reading of previously output information. This mechanism for accessing ports is implemented in the commands: